Cadence Design Systems - San Jose, CA (San Francisco Bay Area)
Job Description
Software development engineer working in a team oriented environment to develop and maintain advanced emulation and co-simulation runtime software tools. Responsibilities include working on Virtual Verification Machine (VVM or SWIT) and VIP debugging for existing and future generation of Palladium emulation system. Responsibilities also include the maintenance of above features in existing and future runtime software tools.
Desired Skills & Experience
Education Requirement:
Bachelor or Master Degree in EE/CS/CE
Recently graduated PhDs are welcome to apply
Skills Requirement:
C/C++, Tcl/Tk and Unix shell programming skills.
Prefer with Multi-threading, RPC and Socket programming experience.
Knowledge with Verilog or VHDL design language and logic design.
Good communication skills and English language proficiency, attention to details, and ability to work in multi-site/multi-person project.
EDA/CAD tool development experience or logic design verification experience expected.
Must Have Current US Work Authorization
We offer a very aggressive financial compensation program, equity participation, and outstanding benefits and 401k programs. All inquiries and responses are held in strictest confidence.
Principals only, no agency or search referrals will be honored!
Company Description
Cadence is the global leader in software, hardware, and services that is driving the transformation of the electronic design automation (EDA) industry. This application-driven approach for creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs , System-On-Chip devices, IP and complete systems at lower costs and with higher quality. Cadence is an equal opportunity employer and is committed to hiring a diverse workforce.
Additional Information
Posted:
May 30, 2012
Type:
Full-time
Experience:
Mid-Senior level
Functions:
Engineering
Industries:
Computer Software
Employer Job ID:
6368
Job ID:
3114920
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